This invention relates to a backmatch resistor structure for an integrated circuit tester.
In the testing of a semiconductor integrated circuit device, a driver is used to apply a voltage signal at a selected high or low level to an input pin of the device under test (DUT) in order to place the DUT in a desired state. It is sometimes desirable to use a transmission line, such as a coaxial cable or a microstrip structure, for signal propagation between an output pin of the tester and an input pin of the DUT. It is well known that it is desirable to backmatch the output resistance of the driver with the characteristic impedance of the transmission line in order to avoid reflections in the signal path between the driver and the input pin of the DUT.
It has been conventional to employ a transmission line having a characteristic impedance of 50 ohms and to use a 50 ohm series backmatch output resistance in the driver to series terminate the transmission line at its source. However, it is difficult to maintain a constant 50 ohm characteristic impedance in practical transmission line structures, and variations of +/-3 ohms are quite common in practical implementations. A 3 ohm error in transmission line impedance results in a 6% initial amplitude error in the pulse delivered to the DUT input pin. An amplitude error of 6% may be greater than the tolerance allowed in testing. Further, the only practical way to produce an accurate 50 ohm backmatch impedance in a driver of the kind described above has been by laser trimming a resistor on the driver circuit, which is complex and expensive. Moreover, a characteristic impedance of 50 ohms is not always optimal.
It is known to use CMOS transmission gates in an SPDT switch configuration to force the output of a driver in a semiconductor tester to selected input high and input low voltage levels, in order to generate a desired pulse waveform for application to the input pin of the DUT. A pullup transmission gate is connected the output of the driver and a rail at the desired high input voltage level and a pulldown transmission gate is connected between the output of the driver and a rail at the desired low input voltage level. A timing generator is associated with each transmission gate for changing its state at accurately controlled times relative to the start of a test cycle.
In CMOS technology, it is not generally possible to obtain both high breakdown voltage and high switching speed, i.e. high speed devices generally have a relatively low breakdown voltage and conversely devices having a high breakdown voltage have a relatively low switching speed.
The pullup and pulldown transmission gates used in the driver described above are active components, in that the waveform at the output of the driver is generated by the switching action of the transmission gates. The transmission gates must have a very rapid switching action in order to generate narrow pulses. This requirement therefore limits the range of voltages that can be applied to the DUT pin by the driver.
It is also desirable in a highly integrated tester, in which relays are not practical due to space constraints, for the leakage current of the driver when disconnected from the tester pin to be low when carrying out parametric measurement unit (PMU) tests, since the leakage current adds to the measurement current and can corrupt the measurement.